• nA level analog system architecture
• Subthreshold digital system architecture and power domain
partitions
• Mixed signal system design to ensure quality and manufacturability
SubVt/NVT Design Methodology
• Corner definition and standard cell characterization
• Timing closuring methodology
• Power optimization
Ultralow power custom IP design
• nA level Analog IPs: DCDC, LDO, POR, oscillator, comparator, bias,
etc
• Digital IPs: Level shifter, retention cells, IO, etc.
• Ultralow leakage PAD design and ESD structure